T 0889/90 19-06-1991

Reasons for the Decision

1. The appeal complies with Articles 106 to 108 and Rule 64 EPC and is, therefore, admissible.

2. The amendments made to the application documents do not contravene Article 123(2) EPC and are, therefore, also admissible.

3. Clarity

3.1. Before considering whether Claim 1 complies with Article 52(1) EPC it is necessary to address the issue of the clarity of the claim. In its communication the Board essentially raised the following three points:

(a) No clear distinction appears to exist between the "initiate peripheral operation" and "peripheral authorising" signals of the first and second control logic means respectively, or between them and the operation of the third control logic means in "granting system bus control to a readied peripheral".

(b) The limitative effect of the second control logic means placing the peripheral authorising signal "in one cycle of the system bus on the output thereof" is not clear. It is, moreover, not clear on the output of what the signal is placed.

(c) The buffering means, although claimed as a separate feature, appear from the description to form part of the third control logic means.

3.2. The Appellant's response to these objections is largely an assertion that Claim 1 is clear. The Appellant further asserts that the signals generated by the respective control logic means are "logically connected together" but are clearly different signals. He then goes on to discuss the operation of the claimed apparatus in terms which are not easy to relate to the invention either as claimed or described. Reference is made to sending a command to the selected peripheral unit when peripheral operation is desired, together with initiation of a memory fetch or store cycle. The address of the needed data is said to be provided on the address bus, together with a "special decode that indicates the unique nature of this memory access". On detection of this special decode the data bus is intercepted, presumably by the peripheral, at the appropriate point in the bus cycle. The correct control signals are thereupon applied to the peripheral unit to enable the desired data transfer.

3.3. It is not clear to the Board what the Appellant means by a "special decode that indicates the unique nature of this memory access"; the claim makes no reference to any "special decode" and the Board can only conclude that the signal being referred to is the special memory access signal (72) which indicates a system/370 memory access and which is specifically referred to at features (e) and (f) of Claim 4. Such a signal is not an explicit feature of Claim 1.

3.4. The Board has, however, been able to interpret Claim 1 by reference to the description (Article 69(1) EPC). From the description it appears that the first logic means of the claim serve to decode the relevant memory-mapped address and to condition the peripheral to accept either a command or data, see page 8, line 29 to page 10, line 4.

3.5. At page 10, lines 5 and 6 it is stated that once the peripheral has been conditioned to accept a command, "the next step is to advise the peripheral of the nature of the command". From lines 6 to 13 of the same page it is clear that by "nature of the command" is meant whether the peripheral is to perform a memory read or a memory write. In this connection, lines 26 to 28 of page 10 and lines 2 to 6 of page 11 refer to setting the write command pin 82 of the peripheral so as to condition it to accept the data it will need to perform its floating point function. When manipulated data is to be transferred from the peripheral to memory the peripheral is firstly advised it should accept a command by appropriately setting its input pin 48 (i.e. the COMMAND/DATA pin) and then the primary processor initiates a peripheral read operation by setting a read enable output, see page 11, line 26 to page 12, line 20.

3.6. It therefore appears to the Board that the peripheral authorising signal of the second control logic means must be interpreted as serving to condition the peripheral to a read or a write mode.

3.7. The reference to the second control logic means placing the peripheral authorising signal "in one cycle of the system bus on the output thereof" must be interpreted, in the light of the description, as referring to placing the peripheral authorising signal on the output of the second control logic means during one cycle of the system bus. It may be that the claim was intended by the Appellant to cover some aspect of a peripheral-to-memory read or write operation taking place within a single system bus cycle, but this is not what the claim states; the Appellant has chosen not to comment on the question of interpretation raised by the Board in its communication.

3.8. The third control logic means are understood as including the buffering means which when enabled permit the peripheral to read to or write from main memory, see page 12, lines 10 to 20 of the description. By control of the buffering means, system bus control is effectively granted to the peripheral.

4. Novelty

4.1. The Board agrees with the Appellant that the single most relevant prior art document is D1. The apparatus known from D1 effects data transfer to and from a selected one of a plurality of memory mapped peripheral devices in a microprocessor implemented data processing system, see Figure 1, in which a bipolar co-processor and "peripherals" are shown. Main storage means are present as in any microprocessor system and these storage means include locations serving as control storage means each having a unique address associated therewith, each of said locations being mapped to a different peripheral device. These features are standard practice in the art, as is the provision of a system bus connecting the microprocessor, peripheral devices and the memory.

4.2. In D1 at page 1, left hand column, heading "Co-processor operation" it is stated that a co-processor "... recognises instructions and data intended for itself. This arrangement is much faster than routing all data and commands through the host. Information is picked off the system bus directly." This is in effect saying that the system can be speeded up by granting direct access of the co-processor to the memory. According to the same page, right hand column, lines 2 to 6, a command to the appropriate address activates the co-processor and sets it up for "the operations and data formats to be handled". According to lines 6 to 9, the co-processor recognises "specified host instructions and retrieves its input data from the bus". The data from the bus must originate in main memory. At lines 16 to 18 a programmable array logic (PAL) device is described which serves "to decode the selected host 'fetch' instruction".

4.3. The mode of operation described above and the presence of the PAL device would be understood by the skilled man to refer to control logic means monitoring the relevant memory locations and serving firstly to detect a call on the co-processor, thereafter to distinguish between instructions and data, in the event of a data operation to set up the co-processor for either a data read or a data write operation and finally to pass control to the co- processor. These are the functions understood by the Board to be carried out by the first, second and (part of the) third control logic means, which are accordingly present in the D1 apparatus.

No mention is made in D1 of buffering means. Claim 1 is accordingly novel with respect to D1.

5. Inventive Step

5.1. It is general practice to buffer devices connected to the system bus and in a case such as a co-processor as disclosed in D1, in which data is fed to the co-processor and then, after completion of the calculations, read back into memory, such buffering must be bidirectional. This necessitates the system hardware recognising when the peripheral is reading data from, or writing data to, the memory and switching the buffer accordingly. The skilled man would find it obvious to provide such buffering in conjunction with the D1 arrangement.

5.2. The Board has accordingly come to the conclusion that the skilled person, implementing the teaching of document D1, would arrive in an obvious manner at apparatus having all the features specified in Claim 1. The subject-matter of Claim 1 does not, therefore, involve an inventive step.

6. The arguments submitted by the Appellant in support of an inventive step are not convincing.

6.1. In the statement of grounds, other than assertions that the second and third control logic means are not present in D1, the Appellant states:

"The significant feature of the invention is to allow the processor to access the cache system for a single piece of data every clock period while simultaneously the cache system continues to accept data being [brought] in from the memory system. Only a single set of address translation and cache tag (directory) hardware is required and, furthermore, only a single- port cache array is required, resulting in significantly less circuitry than the prior art."

The Board is unable to relate this statement to any of the subject-matter of the application. Nowhere does the application refer to a cache system, the peripheral of the described embodiment being a floating point processor apparently of the same kind as in D1. The response to the Board's communication merely repeats the arguments brought forward in the statement of grounds.

7. The Board, therefore, concludes that the subject-matter of Claim 1 lacks an inventive step (Article 56 EPC) and the claim, therefore, fails to comply with Article 52(1) EPC.

8. Claims 2 to 4 must share the fate of Claim 1. Furthermore, they do not appear to include any feature which could involve an inventive step.

9. Finally, even if Claim 1 had as apparently intended been limited to peripheral operation in a single bus cycle, the claim would still have been found to lack an inventive step. The object of the invention is given in the originally filed application at page 3 as being (firstly) the transfer of data between main memory and a peripheral device in only one bus cycle of the main processor, whilst (secondly) avoiding the need to route data through the internal storage area of the main processor during any such transfer.

Any arrangement which achieves the latter object will as a matter of course also achieve the former. Clearly, in D1 direct memory access is granted to the peripheral without intermediate storage. Direct data transfer - as disclosed in D1 - thus implies transfer in a single bus cycle.