T 0299/85 15-06-1988

1. The appeal complies with Articles 106 to 108 and Rule 64 EPC and is, therefore, admissible.

2. The amendments made to the application meet the requirements of Article 123(2) EPC and are, therefore, admissible:

2.1. The claim is, generally, based on the original Claim 2 and, more specifically, restricted with respect of that original claim by such features of the embodiment described with reference to Figure 2 as can be regarded as being significant for the disclosed parallel cascade of log stages having separated amplifier and logarithmic functions and allowing a comparatively wide dynamic range to be achieved.

2.2. The amendments made to the description on 25 June 1984 together with those made at the request of the Board on 15 June 1988 are consistent with the amendemnts to the claim and with the scope of the application as originally filed.

3. No question of lack of novelty arises. Furthermore, the subject-matter of the claim involves an inventive step, for the following reasons:

3.1. In the art of logarithmic amplifiers it is usual to cascade several logarithmic stages.

Basically two different kinds of cascades can be distinguished: a parallel cascade and a serial cascade. The former is represented in D1 Figure 3 and in D3 Figure 3, the latter in D2 Figure 9, in D3 Figure 1, in D4 Figure 2, in D5 Figure 1 and in D6 Figure 4-1. A mixture of both is possible; such a case is represented in D1 Figure 4.

3.2. Depending on the intended application, speed of response is normally a requirement for logarithmic amplifiers, in particular if a signal is an a.c. signal.

In this respect it is well recognised that a parallel cascade is superior to a serial cascade, due to the fact that in a parallel cascade the inputs to all stages have no phase differences whereas in a serial cascade each series amplifier (1 to N in Figure 1 of D5) introduces a small delay. This latter fact being the reason for proposals to compensate such delays (eg. by "delay" in Figure 1 of D5), it is clear that such proposals are irrevelant in cases in which there are inherently no delays, as in a parallel cascade.

3.3. The claimed invention makes use of a parallel cascade and thus of its inherent superiority in response speed.

For this reason, the prior art coming nearest to the claimed invention is considered to be D1, in particular Figure 3 and related parts of that document.

3.4. As a further requirement for logarithmic amplifiers, these must provide for a certain dynamic range of input signals.

In this respect, D1 discloses that its Figure 3 arrangement is limited to 15dB per stage and to a maximum number of three stages.

This limitation is the result of using the kind of log stages proposed in D1.

From the text on page 242 and from Figure 7 and the text relating to it, it can be derived that each log stage amplifies the signal in the signal range below its "active" range, whence it follows that it is an amplifier also at least in the lower part of its "active" range, but that otherwise the differential pairs of transistors used have a logarithmic output current versus input voltage characteristic (cf. Figure 2), whence it follows that signal amplification does not necessarily take place in the upper part of the "active" range, depending, as the skilled person knows, on the impedance of the output circuit.

3.5. As a solution to this dynamic range problem, D1 proposes the Figure 4 arrangement but the skilled person will immediately see that this arrangement is no more a pure parallel cascade and its speed of response will therefore be degraded somewhat unless the delay introduced by the amplifier (a) is compensated, as suggested by D5 Figure 1.

3.6. For this reason, the skilled person may be expected to look for other solutions of the dynamic range problem.

Being aware of the obvious relation of the limitations of the Figure 3 arrangement to the kind of log stages used (cf. 3.4) he will consider avoiding the combination of amplifying and logarithmic conversion functions in these stages.

A model for doing so is known to him in the form of the Figure 3 arrangement of D3, this arrangement using separate amplifying and logarithmic converting means in each log stage. Obviously by this separation each function can, independent of the other, be optimised and for this reasons, the skilled person can be expected to consider using a separate amplifier and logarithmic converter in each stage, knowing also that this does not degrade in any way the inherent speed of response advantage of the parallel cascade.

3.7. He will clearly not be deterred from such consideration by the mere fact that D3 relates to logarithmic amplifiers converting a.c. into d.c. which therefore have detectors in their log stages. It will be very clear to him from his general knowledge that, for achieving an a.c. output, he would only have to omit these detectors.

3.8. The invention as now claimed goes however beyond such considerations.

3.9. First, it proposes to use, as logarithmic converter, a series arrangement of diodes biased by a driver circuit, whereby the signal is fed to, and taken from, the node common to the diodes.

As regards this feature, the following is noted:

No diode arrangement is used in D1.

D3 discloses, as an example of a logarithmic converter, a parallel arrangement of differently biased diodes; no incentive to modify this arrangement can be derived from D3.

The serial diode arrangement used in the amplifier stage shown in Figure 13 of D2 has quite a different function. It serves only to switch, at a particular input signal level, the amplification of the respective stage to 0dB. The logarithmic conversion is not effected by these switches but by the combined characteristic of several stages.

Nothing relevant can be derived from D4, D5 or D6.

D7 shows a logarithmic amplifier comprising, in parallel cascade, a first log stage with an amplifier and a logarithmic converter and a second log stage consisting only of a logarithmic converter. In these logarithmic converters, use is made of an anti-parallel diode arrangement biased by a stabilised current to exhibit a logarithmic volt-ampère characteristic.

It may be the fact that a serial diode logarithmic converter as claimed is, in effect, equivalent to that anti-parallel diode arrangement, but there is no disclosure of this equivalence in the prior art citations and, even if there were any, the claimed invention comprises more than the replacement of one arrangement by an equivalent.

3.10. As a further feature, the claimed invention employs an anti-parallel diode arrangement reducing overshoot in the amplifier cut-off output.

As to this feature the following is noted:

The only citation disclosing an anti-parallel diode arrangement is D7. However, that arrangement is biased so as to have a logarithmic function. No incentive to use such an arrangement for the quite different purpose of reducing overshoot can thus be derived from D7.

Furthermore, even on the assumption, previously made in a communication by the Board and not challenged by the Appellant, that anti-parallel diode arrangements for reducing overshoot are general knowledge per se, it does not necessarily follow that the particular arrangement now claimed in combination is obvious.

3.11. The claimed invention must be seen as a whole.

Putting its various pieces together and comparing that combination with the prior art, the invention presents itself in the following way:

Starting from a parallel cascade of log stages (D1 Figure 3):

(a) Instead of differential amplifiers (Figure 2 and 7) as log stages, separated amplifiers and logarithmic converters (as in D3 Figure 3) are used;

(b) The amplifiers are supplemented by anti-parallel diodes reducing overshoot;

(c) Instead of anti-parallel diodes (as in D7) or any other kind of circuit as logarithmic converters, a properly biased serial diode arrangement is used (only known per se from D2 in a function which is not comparable to the one used here).

3.12. Whether or not it is obvious to apply one or two of these features in a logarithmic amplifier of the kind in question, it is only relevant to the present case whether it is obvious to combine all three.

In deciding on this point, also the results of this combination must be considered.

In this respect, the following is noted:

It has been submitted that the embodiment shown in Figure 2 allows a dynamic range of 35dB per stage to be achieved. The Board has no reason to doubt the correctness of this submission. Further, the Board is satisfied that this quantatitive result is the result of the essential technical features of that embodiment which consists in (a) the use of separate amplifiers, (b) reducing any overshoot in their output, (c) the use of a properly biased series diode arrangement as logarithmic converter.

In contrast, D1 discloses the achievement of only 15dB per stage and no higher values are disclosed in any other prior art citation (including D4 and D5).

An improvement by 20dB must be regarded as outstanding and unexpected, even if some improvement could be expected from the application of feature (a) alone (cf. paragraph 3.6).

It is therefore to be taken as an indication that the claimed combination of features does involve an inventive step.

4. In accordance with Rule 67 EPC, reimbursement of an appeal fee shall be ordered when a Board of Appeal deems an appeal to be allowable "if such reimbursement is equitable by reason of a substantial procedural violation." In the present case, the Appellant asserts that there was such a violation (in contravention of Article 113(1) EPC) in that, both when announcing its decision at the end of oral proceedings and in the written reasons for decision, the Examining Division made and relied upon the assertion that phase difference generated in the a.c. amplifiers of D3 would have an effect on the d.c. output signal. In the written reasons for decision this was stated to be "self evident". Nothing in the file of the case shows that this point was ever raised in writing or orally with the Appellant prior to the announcement of the decision. Prima facie, therefore, this was an assertion of technical fact which should have been discussed with the Appellant (who disputes it) before the decision was announced and the Examining Division's failure to do so amounted to a breach of the requirements of Article 113(1) EPC. However, this does not seem to have been a major point in the decision under appeal and is not a point on which the present appeal is being allowed. Indeed, without the substantial amendments in the main claim now made, the appeal could not have been allowed. In these circumstances, the Board is unable to conclude that reimbursement would be equitable by reason of a substantial procedural violation. Accordingly, reimbursement of the appeal fee cannot be ordered.