T 0050/83 29-03-1989

I. The European patent application No. 79 301 138.8 (publication number 0 006 351) was refused by decision of the Examining Division, dated 6 September 1982.

II. The reason for the decision was that, having regard to the state of the art disclosed in US-A-4 068 266, the novelty of the claimed method was limited to its being operated on a block by block basis and that such was also the case for the particular example described in the cited document with reference to Figure 2. No inventive step, therefore, could be perceived in the subject-matter of Claim 1.

III. The Appellant lodged an appeal against the decision by telex of 8 November 1982 and paid the corresponding tax on the same day. The telex was confirmed by letter received 11 November 1982. The grounds for appeal were submitted by telex on 17 January 1983 and that telex was confirmed by letter received on 20 January 1983.

IV. In response to communications from the Board, the Appellant filed on 25 February 1989 new description and claims replacing those on file.

The new Claim 1 reads as follows:

"A method of processing image pixels derived by scanning an original image line by line to provide additional, intermediate, lines of image pixels using existing lines of image pixels, including the steps of:

(a) buffering blocks of image pixels from the first and second existing lines of image pixels to provide an address;

(b) addressing a memory storing discrete image outputs with said address to obtain the output corresponding to said address;

(c) using the image output obtained from said memory to construct a portion of at least one intermediate line;

(d) outputting one of said existing lines and said intermediate line or lines;

(e) repeating steps a, b, c and d using succeeding blocks of image pixels from said first and second lines to construct said intermediate line or lines until a complete existing line and the intermediate line or lines have been output;

(f) repeating steps a-e using the second and third existing lines to construct a second intermediate line or lines; and

(g) repeating step f for each succeeding pair of existing lines; the method being characterised in that

(h) said buffering of said blocks of image pixels to provide an address is carried out on a block-by-block basis, said image pixels being shifted through a buffer by a plurality of pixels at a time;

(i) the image outputs in the memory are predicted image pixel patterns comprising matrix patterns of image pixels of the same width as said plurality of pixels, there being one row of pixels in said matrix patterns for each intermediate line to be constructed;

(j) said intermediate line or lines are constructed by successive ones of said matrix patterns of image pixels with the same timing relationship as said blocks of image pixels; and

(k) each intermediate line or set of lines is output simultaneously with and separately from the preceding existing line, with the pixels of each intermediate line or set of lines in synchronism with the pixels of the preceding existing line."

The appended Claim 2 relates to a method according to Claim 1, characterised by the additional step of buffering image pixels from the existing lines equal to the said plurality of pixels plus additional image pixels from said existing lines to provide an expanded address.

V. During a conversation by telephone held on 9 March 1989, the rapporteur of the Board drew the Appellant's attention to a few clerical errors and to the lack of reference to the US-A-4 068 266 in the new pages of description and proposed appropriate amendments thereof. The Appellant assented to said amendments.

VI. The Appellant requested the impugned decision to be set aside and a European patent to be granted on the basis of the following documents:

- description, pages 1-7 received on 25 February 1989, with the amendments agreed to during the conversation by telephone of 9 March 1989.

- Claims 1 and 2 received on 25 February 1989, and

- drawings, Figures 2, 5-11 of the published patent application, to be re-numbered 1-8.

VII. To support his view, the Appellant substantially argued as follows:

(1) Although the addresses for interpolator (32) in the US-A-4 068 266 are formed by blocks of pixels, the pixels are shifted one pixel at a time through the register (31). According to the invention, a plurality of pixels are shifted at a time, whereby the advantage of quicker handling of a line of pixels is provided.

(2) In the method of the cited document, the video output consists of alternate complete lines of data. According to the claimed invention, the output consists of one or more intermediate lines which are output simultaneously and in synchronism with the pixels of the preceding existing line. Ability for rapid printing out of data is thereby provided and, even if the multiplexer were removed from the system disclosed in the US-A-4 068 266, said system would not be able to achieve the same results.