T 0239/08 19-10-2012

I. The patent proprietor appealed against the decision by the opposition division maintaining European patent No. 0 948 792 in amended form on the basis of the then first auxiliary request which differed only in claim 7 from claims 1 to 11 as granted.

II. An opposition had been filed requesting revocation of the patent in its entirety on the grounds for opposition pursuant to Article 100(a), (b) and (c) EPC 1973 (lack of inventive step, added subject-matter and insufficient disclosure of the invention according to claim 7 as granted, respectively).

III. The opponent appealed against the decision to maintain the patent in amended form and requested that the patent be revoked, on the grounds of lack of inventive step and added subject-matter (Articles 100(a) and (c) EPC 1973, respectively).

IV. The appellant replied and requested that the appeal be dismissed.

V. The following prior-art documents were referred to:

D1: JIN-MAN HAN et al.: "Skew Minimization Techniques for 256M-bit Synchronous DRAM and beyond", 1996 Symposium on VLSI Circuits Digest of Technical Papers;

D2: US 5,267,214 A;

D3: US 5,251,176 A;

D4: US 5,586,078 A;

D5: US 5,596,521 A; and

D6: US 5,384,745 A.

VI. In an annex to the summons to oral proceedings, the board observed inter alia that the interpretation of the last feature of the preamble of claim 1 (sense amplifier/s "coupled to") seemed of significance for the question of whether claim 18 as originally filed could be considered as a basis for claim 1 and whether the omission of a feature of original claim 18 relating to the determination of a memory bank associated with a requested address constituted an unallowable amendment. The board also made observations on the different prior art documents.

VII. Neither party commented on the board's observations in the annex to the summons, but they both announced in writing that they would not be attending oral proceedings. Thus the oral proceedings took place on 19 October 2012 in their absence.

VIII. Claim 1 reads as follows:

"A memory device comprising:

a first memory bank (BANK0) including at least one subarray (62a) of memory cells, the first memory bank having a first row decoder (64) and a first column decoder (76);

a second memory bank (BANK1) including at least one subarray (80) of memory cells, the second memory bank having a second row decoder and a second column decoder (78);

a first plurality of sense amplifiers including at least one sense amplifier (70) coupled to one memory subarray (62a) in the first memory bank and coupled to one memory subarray (80) in the second memory bank

characterised in that

a control mechanism is configured to determine whether the sense amplifier (70) is already in use; and access the data if the sense amplifier (70) is not already in use to avoid simultaneous access to memory subarrays that share the sense amplifier (70)."

IX. Claim 9 reads as follows:

"A method for accessing data stored in a memory device,

wherein the memory device includes at least two memory banks that share at least one sense amplifier (70), the method comprising the steps of:

(a) receiving a request to access a particular address; and

(b) determining a memory bank associated with the requested address;

characterized by the steps of

(c) determining whether the sense amplifier (70) associated with the memory bank determined in step (b) is already in use; and

(d) accessing the data associated with the requested address if the sense amplifier (70) associated with the memory bank determined in step (b) is not already in use."

X. As regards added subject-matter, the reasoning in the decision under appeal may be summarised as follows:

Originally-filed claim 18 forms the basis of claim 1. It recites a step of "accessing the data ... if sense amplifiers associated with the memory bank ... are not already in use". It is thus necessary to check whether all sense amplifiers associated with the selected memory bank are available for use, before accessing data (see also figure 6 and page 11, lines 28 to 31 in the application). Claim 1 does not include the availability check of the other associated sense amplifiers and the condition that the other associated sense amplifiers are available.

No other interpretation of claim 1 is possible than relating "the sense amplifier (70)" of the characterising portion of claim 1 with the shared "at least one sense amplifier (70)" in the preamble, in the light of the description and in order to solve the technical problem posed.

The goal of the invention is to prevent simultaneous access to memory banks sharing sense amplifiers. Hence, checking the availability of the shared sense amplifiers between the two memory banks is sufficient, because the other sense amplifiers of the selected memory bank are not shared and hence are available for use. Checking the availability of other, non-shared, sense amplifiers was never explained as essential in the original disclosure. Furthermore, the removal of this latter check requires no modification of other features. The three-step test according to the Guidelines for Examination, C-VI, 5.3.10, is thus successful.

Furthermore, both original claim 18 and present claim 1 focus on a memory device comprising two memory banks and at least one shared sense amplifier between the two banks. Claim 1 does not mention a third memory bank, with one sense amplifier shared between the second and third memory banks, so that an additional check of this shared sense amplifier is not necessary to access the second memory bank.

Consequently, the amendments in claim 1 (and the corresponding method claim 9) do not extend beyond the content of the application as filed.

XI. As regards added subject-matter, the appellant essentially argued as follows:

Claim 1 is not limited to a device with only two memory banks, although it does not expressly mention a third bank. Sense amplifiers not shared between two subarrays in the two banks are also not specified. For example, claim 1 does not preclude one or more of these remaining sense amplifiers from being shared between one (BANK1) of the two banks recited in claim 1 and a third bank (BANK2 in figure 4). According to claim 1, if the shared sense amplifier (70) is not in use, then the first memory bank is accessed. A further check of the at least one sense amplifier (82) shared with the third bank is however described as necessary prior to accessing the second bank. The result is that the embodiment of figure 4 of the patent in suit is not excluded by the wording of claim 1, but that the reduced functionality of claim 1 is not supported for that embodiment.

By contrast, claim 18 of the application as originally filed, on which present claim 1 is based, determines whether all sense amplifiers associated with the memory bank in question are not in use before allowing access to requested data. So, claim 18 also prevents simultaneous access to memory subarrays that share more than one sense amplifier such as in the embodiment of figure 4. This shows that the scope of claim 18 has been broadened during the examining proceedings, adding fresh subject-matter.

A positive answer to any one of the questions in the three-step test formulated in decision T 331/87 results in the finding of added subject-matter. In the present case, claim 1 fails the first step of the test, because the features removed were explained as essential.

XII. As regards added subject-matter, the respondent's arguments additional to those in the decision under appeal may be summarised as follows:

The embodiments of figures 2 and 4 in the patent in suit avoid simultaneous access to memory subarrays which share at least one sense amplifier of the plurality of sense amplifiers if the at least one shared sense amplifier is already in use by another memory subarray. It is irrelevant whether the memory subarrays are coupled to another plurality of sense amplifiers within the same memory bank (embodiment of figure 2) or also to another plurality of sense amplifiers of another memory bank (embodiment of figure 4).

Features such as further pluralities of sense amplifiers not shared between the banks (embodiment of figure 2) or further pluralities of sense amplifiers shared by different adjacent banks (embodiment of figure 4) are neither required nor excluded by claim 1 as filed or as maintained, or by any other claims as filed or as maintained. Moreover, such features are completely irrelevant to the present invention, since to implement the present invention it is sufficient to consider just the at least one shared sense amplifier of the plurality of sense amplifiers and the two memory subarrays of the two memory banks which are both coupled to the at least one shared sense amplifier.

The appellant's assumptions are purely hypothetical in that they are based on scenarios which are not excluded by the wording of claim 1, or on facts and features which are not included and expressed by the wording of the patent in suit. Furthermore, according to claim 1, the whole "first plurality of sense amplifiers" is shared, not just the "at least one sense amplifier (70)". There are no remaining sense amplifiers which could be coupled to a third memory bank.

XIII. As regards inventive step, the reasoning in the decision under appeal may be summarised as follows:

D1 discloses a device according to the preamble of claim 1, in particular with one of the amplifiers (IO S/A) being the shared "at least one sense amplifier" of claim 1. D2 discloses a mechanism controlling the connection between sense amplifiers and memory blocks but does not disclose a mechanism determining whether sense amplifiers are already in use. None of the available prior-art documents discloses a control mechanism configured to determine whether the at least one shared sense amplifier is in use and to access the data if the at least one shared sense amplifier is not already in use, as defined in claim 1.

The person skilled in the art would only have provided sequential access to the memory banks sharing the same sense amplifier. Furthermore, the opponent's examples based on every-day behaviour of people sharing an object reflect an ex post facto analysis, in selecting one of a plurality of alternatives: two persons could agree to use a shared object at different times instead of checking the availability of the shared object. Moreover, every-day behaviour cannot be applied directly to the field of memory banks without exercising an inventive step. Thus the subject-matter of claim 1 is inventive.

XIV. As regards inventive step, the appellant essentially argued as follows:

The subject-matter of claim 1 lacks an inventive step in view of the teaching of D1 at least. Figure 1 of D1 discloses a memory device, in particular with input/output sense amplifiers shared between two adjacent memory banks. Such amplifiers differ from bit line sense amplifiers described in the patent in suit. The definition of the sense amplifiers in claim 1 is however a general one.

The problem of minimising die area and thus cost is solved by sharing sense amplifiers between memory banks within a memory device. It was known at the priority date of the patent in suit to share sense amplifiers, and thus to save die space and cost, on an inter-memory (bank) level as well as on an intra-memory (subarray) level. Furthermore, D1 inherently discloses a control mechanism but is silent regarding its operation. The objective technical problem to be solved with regard to the closest prior-art document D1 is therefore how to configure the control mechanism to avoid simultaneous access to memory subarrays that share the sense amplifier.

It was well known that banks in a multiple-bank memory device were independent and that each memory bank within a memory device was capable of being operated and accessed simultaneously and separately from the other memory banks in the device. This is shown in D6 and also acknowledged in the patent in suit.

The memory device of D1 is such a multiple-bank memory device, with memory banks which can be accessed simultaneously. When multiple memory access requests are received simultaneously by the memory controller, these requests include access requests for adjacent banks that share sense amplifiers.

It was well known in the art that collisions in the use of shared sense amplifiers were to be avoided by controlling the shared sense amplifiers such that they are connected to only one of the blocks of memory between which they are shared when memory access utilising that shared sense amplifier is under way. This is exemplified in D2, which discloses a memory device split into memory blocks, with bit-line sense amplifiers shared between adjacent blocks. Sense amplifier control signals are generated by a circuit (figure 10 and the associated description) to connect the shared sense amplifiers to one block and to disconnect them from the other blocks to which they may be connected. Thus the sense amplifiers are controlled to avoid simultaneous access to the blocks to which they are connected. This form of control is also exemplified in D3 and D4. Another example of sense amplifiers being shared between memory banks in a memory device may be found in figure 7 of D5, which is prior art for the reason that the earliest priority is not validly claimed in the patent in suit.

Obviousness is also demonstrated as follows. The immediate reaction of any person presented with the objective technical problem of how to avoid simultaneous use by multiple users of a shared item is to have a prospective check as to whether the shared item is already being used before commencing use, and to commence use only if the shared item is not in use by another user. Various examples of this "every-day life behaviour" exist. One such example is the sharing of a PC by two research students in a university. Another example is the sharing, between two or more people, of a portable disc drive for a PC or laptop computer. This behaviour is routine and transferable across technical fields, and the skilled person is no different to any other person in this respect.

For these reasons, claim 1 is not inventive.

XV. As regards inventive step, the respondent stated that the analysis in the decision under appeal was correct and referred to the arguments presented in the opposition proceedings.