T 0654/92 03-05-1994

1. The appeal is admissible.

2. Amendments

The Board is satisfied that the amendments to the claims do not extend beyond the content of the application as filed or cause the protection conferred to be extended. The claims of all three requests therefore comply with Article 123(2) and (3) EPC.

3. Clarity of Claim 1

3.1. Claim 1 of the main request includes "means for changing a duty cycle of a horizontal drive pulse such that the duty cycle increases when the horizontal frequency becomes higher". The duty cycle of transistor 37 is in both the Figure 7 and Figure 11 embodiments arranged to decrease with increasing frequency, as might be expected since the effect of the storage time is to add an overhead to the switching time which with increased speed becomes a progressively larger fraction of the overall switching time; a decrease in duty cycle is therefore necessary.

3.2. It is noted that Claim 1 of both auxiliary requests as well as Claim 8 of all requests refer to changing a duty cycle of a horizontal drive pulse "for the drive stage (36)". Implicit in this claim is therefore a phase inversion in stage (36). Claim 1 of the main request has accordingly been interpreted as also requiring such a phase inversion, the duty cycle of the drive pulse accordingly being meant in the claim.

4. Prior art

4.1. Although A4 is acknowledged in the patent (paragraph bridging columns 5 and 6), most of columns 1 to 6 and part of column 7 are taken up with a discussion of Figures 1 to 6, described as a "previously proposed" receiver. In the course of the oral proceedings it became clear that this receiver did not form part of the state of the art within the meaning of Article 54(2) EPC but was a receiver developed within the Respondent's company and not made public at the claimed priority date.

4.2. The Board notes that the English version of Rule 27(1)(b) requires an applicant to "indicate the background art which, as far as known to the applicant, can be regarded as useful for understanding the invention...". In this Rule the expression "background art" is, in the Board's view, to be interpreted as background prior art, i.e. art within the meaning of Article 54(2) EPC. This is the only reading consistent with the French and German versions of the Rule, which refer to "l'état de la technique antérieure" and "Stand der Technik" respectively.

4.3. The practice of starting out from art which is known to the applicant but which was not public at the claimed priority date is accordingly inconsistent with the requirements of the EPC. Any such art must be ignored in an assessment of inventive step.

4.4. Thus, the Board does not consider that the internal prior art cited in the application is the correct starting point for the invention. This prior art moreover appears to be based on the artificial premise that the skilled man would seek at all costs to maintain a constant duty cycle. The argument was inter alia advanced at the oral proceedings that the skilled man, finding that a device with a 50% duty cycle did not work properly at the higher frequency, would seek to experiment with different duty cycles in order to arrive at one which would be satisfactory at both lower and higher scan rates. As explained below, the Board was not able to accept this argument.

5. Novelty and Inventive Step (Main Request)

5.1. In television line output stages the beam must be swept across the screen at a constant rate and thereafter quickly return to the start during the retrace or flyback period. This requires a sawtooth waveform to be supplied to the scan coils. In early television receivers such a waveform was generated by a sawtooth oscillator and supplied to the scan coils by way of a driver amplifier, but such an arrangement is inappropriate for a solid state output stage in which the driving device is a switch. Thyristors or high voltage transistors are generally used in conjunction with a series resonant circuit formed by the scan coils and a capacitor, together with a freewheeling diode in parallel with the transistor. By appropriate switching of the transistor a linear current flows through the scan coils and by turning the transistor off at the appropriate point in the cycle the LC circuit rings and the flyback is effected.

5.2. In such circuits a particular problem arises from the phenomenon of transistor storage time Ts, a problem well known per se in the transistor art before the priority date. In high-voltage transistors as used in television line output stages storage time problems are particularly acute; in such devices the high voltages used require a substantial physical thickness of the semiconductor, so that on switching off there is a delay - caused by carrier recombination - in the ending of the base current, the base current and hence the collector current tapering off comparatively slowly rather than ending abruptly. In a multiple scanning type television receiver with fixed charge/discharge and flyback periods, i.e. a constant switching duty cycle, the high- voltage transistors used in the line output stage can at high scanning speeds give rise to a situation where the output transistor is conducting during the flyback time, causing misoperation.

5.3. It was common ground at the oral proceedings that the most relevant single prior art document is A4. In the Board's view this document rather than the internal prior art (see point 4 above) is the correct starting point for an assessment of novelty and inventive step. A4 describes a multiple scanning type television receiver of the above-described kind which is designed for two line frequencies, one a double of the other, and having the features of lines 1 to 11 of Claim 1 as set forth above. The driver circuit is similar to that used in the internal prior art shown in Figures 2 and 4 of the patent. The document makes no reference to any problems caused by storage time and is primarily concerned with the synchronisation of scan rate with power supply switching.

5.4. The subject-matter of Claim 1 differs from this prior art in having the following additional features:

(a) Frequency detecting means;

(b) Control means connected to the frequency detecting means and the horizontal deflection circuit; and

(c) Means for changing the duty cycle of a horizontal drive pulse with frequency.

The subject-matter of Claim 1 is accordingly novel.

5.5. The first two features in effect state that a change in horizontal scanning frequency is detected automatically and the line output oscillator frequency controlled accordingly. In A4, manual switching is provided. However, the automation of operations formerly performed manually is a well known aim of industry. It has long been a trend in the TV art to simplify the control of a receiver for the end user; thus the skilled man could be expected to seek to replace any manual adjustment by an automatic one, which in the context of the A4 receiver would require the provision of automatic switching. No inventive step is thus involved in the provision of features (a) and (b) in the A4 receiver.

5.6. Feature (c) indicates that the duty cycle of the horizontal drive pulse is dependent on the line frequency of the received TV signal. As noted at paragraphs 3.1 and 3.2 above the drive pulse has a polarity such as to render the switching transistor non- conducting when the signal is high and conducting when it is low; an increase of the duty cycle of the drive pulse therefore implies that the switching transistor is either in the off state or about to enter it for a comparatively longer time; although not explicitly stated in the claim, this increase in duty cycle is intended to be at the higher line frequency. As noted at paragraph 5.2 above, the delay in turning off caused by the storage time of the transistor can be considerable and can account for a relatively long portion of the high level of the drive signal. The situation can therefore arise that the switching transistor is rendered conductive too early during the scan, even before the flyback has ended, resulting in malfunctioning of the circuit.

5.7. The Respondent submitted during the oral proceedings that although the skilled man would not neglect the storage time of the switching transistor when designing the drive pulse circuitry, he would not opt for the solution according to the invention, i.e. a drive signal with a duty cycle which varies with the line frequency, but would rather select a specific duty cycle which did not need to be changed when switching from one line frequency to another. It was demonstrated at the oral proceedings how, by choice of a suitable duty cycle, the skilled man could meet all circuit constraints at least for the case where the line frequencies do not differ by more than a factor of 2. The skilled man, implementing the A4 circuit, would therefore maintain duty cycle at this constant value independent of scan rate.

5.8. The Board is unable to accept this argument, which is based on the assumption that the skilled man has attached primary importance to maintaining a constant duty cycle. Nothing in the prior art suggests this. A4 is silent on the nature of the oscillator generating the drive pulse. The Respondent has submitted that the skilled man would therefore assume that the duty cycle is not changed; the Board, however, takes the view that the silence merely means that the skilled man is considered capable of providing a suitable circuit without the exercise of inventive skill.

5.9. From prior art documents such as A2, a data sheet for integrated circuit line scan controllers, and A5, which represents a university lecture to students and therefore can be considered part of the common general knowledge, it is clear that the skilled man was at the priority date well aware that the main switching transistor should be rendered non-conducting when the forward scan is completed, thus triggering the line flyback, and should subsequently be rendered conducting at some time during the first half of the next line scan. A2 and the prior art document A3, also a data sheet for integrated circuit line scan controllers, both permit a variable duty cycle, 40-60% in the former case and 0-98% in the latter, 50% being in the middle of both ranges which could be taken to suggest that it is the preferred value. (Since these ranges are substantially symmetrical they apply both to the drive pulse and the main switching transistor.) The Board has no reason to doubt the statement in the description of the patent that the value of the duty cycle in a standard receiver is about 50% (column 5, lines 49 to 56), or the assertion made by the Respondent in the course of the oral proceedings that by changing the duty cycle of the drive pulse to a value in the region of 60% a constant duty cycle can be maintained for different scan frequencies.

5.10. However, in the above-mentioned prior art it is not suggested that the duty cycle as such is a primary control parameter. It appears rather that the primary parameter in a line output circuit is not duty cycle but pulse width and is determined primarily by the flyback period and switching delays, periods both essentially independent of scan rate. It is noted that according to A4 the retrace time is 6 ms for both TV standards. Indeed, as the Respondent's representative himself admitted at the oral proceedings, switching can take place at any time after the end of the flyback period and before the zero crossing of the scan itself.

5.11. Thus, when the skilled man is faced with the problem of determining a suitable pulse form for controlling the switching transistor in a multiple scan rate receiver, his primary concern must be that, independent of the line frequency, the transistor should open and close at appropriate times. The minimum time the transistor must remain non-conducting is as noted at paragraph 5.10 above determined by largely constant factors such as the storage time of the transistor and the flyback time. The rest of the pulse cycle, however, will depend on the scanning period; if the line frequency is high, the scanning period is short and therefore the drive pulse duty cycle would require to be higher. It follows that an increase in line frequency will automatically lead to an increase in drive pulse duty cycle if the designer, when going from one line frequency to another, tries to maintain the correlations between the horizontal yoke current and the opening and closing times of the switching transistor. In the Board's view, the prior art indicates that he would indeed have this in mind.

5.12. The Board considers that the skilled man, seeking to implement the circuit shown in A4 would have as a primary object the need to ensure that switching takes place after a time determined by the flyback period and switching delays, a period which as noted above is essentially independent of scan rate. He would thus without the exercise of invention construct a circuit having feature (c) of Claim 1. The subject-matter of Claim 1 accordingly does not involve an inventive step.

6. Novelty and Inventive Step (Auxiliary Requests)

6.1. Claim 1 of each of the auxiliary requests merely adds to Claim 1 of the main request features which render more precise the operation of the receiver but which are either known in the prior art or obvious modifications.

6.2. Thus, A4 discloses the provision of an oscillator operable in synchronism with the horizontal synchronising signal and has a horizontal deflection circuit including an output switching device coupled to the oscillator via a drive stage. If for the reasons given above the skilled man were to arrange for a horizontal drive pulse whose duty cycle is changed he would supply this pulse to the drive stage. The subject- matter of Claim 1 of the first auxiliary request accordingly lacks an inventive step.

6.3. In any workable line output stage the driving period of the horizontal drive pulse must be maintained for a period which exceeds the sum of a storage time of the output switching device and the retrace time by a predetermined time period. This feature is accordingly merely a statement of the obvious and the subject-matter of Claim 1 of the second auxiliary request also lacks an inventive step.

7. Since Claim 1 of each request has been found not to be allowable it has not been necessary to consider the remaining claims of each request, in particular Claim 8, the Patentee not having requested that these claims be considered per se.